This invention relates generally to CMOS integrated circuits and more particularly, it relates to a TTL output driver gate configuration which has reduced voltage spikes on internal power supply potential and ground potential nodes.
In common practice, it is often required to use more than a single circuit type or logic type in an electrical system. For example, a complementary metal-oxide-semiconductor (CMOS) central processing unit may interface through busses with peripheral units adapted to receive transistor-transistor-logic (TTL) levels. Thus, there has been provided heretofore output buffer circuits which enable integrated circuits to receive CMOS input logic levels and to provide output signals that are TTL compatible. The output buffer circuit generates, when enabled, an output signal which is a function of a data signal received from other logic circuitry of the integrated circuit.
Output buffer circuits typically use a pull-up transistor device and a pull-down transistor device connected in series between first and second power supply terminals. The first power supply terminal may be supplied with a positive potential +V, which is connected to an internal power supply potential node. A second power supply terminal may be supplied with a negative potential -V or a ground potential, which is connected to an internal ground potential node. The connection point of the pull-up and pull-down transistor devices is further joined to an output terminal or pad.
Dependent upon the logic state of the data input signal and an enable signal, either the pull-up or pull-down transistor device is quickly turned ON and the other one of them is turned OFF. Such rapid switching ON and OFF of the pull-up and pull-down transistor devices causes sudden surges of current (di/dt or current spikes) in the power supply and ground lines due to parasitic packaging and interconnect inductance and resistance. Also, during output switching, charging and discharging currents from the pull-up and pull-down transistors driving large capacitive loads exists. These transient currents (current surges and charging/discharging currents) will flow through the inductive and resistive components of the power supply and ground lines so as to cause voltage spikes at the internal power supply potential and the internal ground potential nodes of the output buffer.
These voltage spikes are undesirable since they will degrade the output logic "1" and logic "0" voltage levels causing interfacing problems among the output buffer circuit and other integrated circuits. These undesirable voltage spikes at the internal power supply potential and ground potential nodes are sometimes referred to as "ground bounce." The "ground bounce" will be more severe when many output buffers are switched simultaneously to the same logic state, are operated at higher speeds, or are used to drive larger external capacitance loads. Under such circumstances, the voltage spike may be large enough to cause input buffers to change logic state and output buffers attempting to drive a logic "0" to go to a higher voltage level, thereby resulting in an erroneous operation.
In the design of output buffers, a trade-off is known to exist between achieving high-speed/high-drive operation and minimizing of the transient currents. While there have been attempts made in the prior art of output buffer design to achieve higher speed and higher output drive currents by increasing the sizes of the output pull-up and pull-down transistor devices, this has resulted in the disadvantage of increasing the voltage spikes. In other words, in order to minimize the voltage spikes for the prior art output buffer designs, the high-speed and/or high-drive characteristics was required to be sacrificed.
It would therefore be desirable to provide a TTL output driver gate configuration which has reduced voltage spikes on internal power supply potential and ground potential nodes with only a small speed penalty. The output driver gate configuration of the present invention includes a pull-up transistor and a pull-down transistor whose gates are made serpentine and are driven at only end thereof. The reduction of voltage spikes is achieved by slowing down the turn-on times of the pull-up and pull-down transistors during transistions by means of the distributed resistances and capacitances of the polysilicon material used to form the gates thereof.